With continuous development of semiconductor manufacturing technologies, the density of devices per unit area and computation speeds of elements within an integrated circuit also grow exponentially. According to Moore's Law estimates, the number of transistors in a central processing unit (CPU) of a computer has currently exceeded seven billion. In order to achieve such high densities, sizes of fundamental elements within an integrated circuit continue to reduce significantly. For example, in a metal-oxide-semiconductor field-effect transistor (MOSFET), a decisive factor influencing the size reduction of individual elements is the gate structure definition.
In U.S. Pat. No. 7,078,300, a method for manufacturing a thin germanium oxynitride gate dielectric layer on a Ge-based material is disclosed. The method involves two manufacturing steps. In the first step, nitrogen is incorporated into a surface layer of the Ge-based material. In the second step, the nitrogen-incorporated Ge-based layer is oxidized. In the method, the nitrogen-incorporated Ge-based material is exposed in an oxygen-containing environment to yield excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors.
To keep current manufacturing processes of germanium MOS structures cost-effective, a germanium film is usually grown on a silicon substrate, and a gate dielectric layer is formed on the germanium film, followed by forming a gate electrode layer on the gate dielectric layer to complete the manufacturing of a gate structure. A patterning step is then performed to produce the required channel length.
However, the above method suffers thorny interface issues that are described below.
First, the difference between lattice constants of germanium and silicon is about 4.2%, meaning that a substantial compressive strain is induced when a germanium layer or a silicon-germanium alloy layer is grown on the silicon substrate. As the thickness of the germanium layer or the silicon-germanium layer exceeds a “critical” thickness, stress relaxation takes place by the generation of interfacial defects known as misfit dislocations. Further, in order to minimize the impact of these defects caused by stress relaxation on the device characteristics and performance, not only is an additional germanium buffer layer to be grown, but also a high-temperature annealing process is often required.
Second, as compared to the stable interface that exists between silicon and silicon dioxide, the oxide of germanium, GeO2, is quite soluble in water and thermally unstable when exposed to high temperature (as in the annealing process). Thus, additional interfacial defects are likely introduced during the subsequent cleaning and high-temperature processes, leading to a rough interface with undesirable interfacial properties.
Therefore, there is a great need for a solution that effectively overcomes the above critical issues.